1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a Split Gate (Flash) Electrically Erasable Programmable Read Only Memory (EEPROM) and a method for manufacturing the same.
2. Discussion of the Related Art
A typical example of a nonvolatile memory device, which has electric program and erase functions, is a (flash) EEPROM (Electrically Erasable Programmable Read Only Memory) cell. Such (flash) EEPROM cells may be classified into a stack structure and a split gate structure.
FIG. 1 shows a cross sectional view of a stack type EEPROM cell according to the related art. FIG. 2 shows a cross sectional view of a split gate type EEPROM cell according to the related art.
As shown in FIG. 1, the stack type EEPROM cell according to the related art includes a p-type semiconductor substrate 1, a tunneling oxide layer 2, a floating gate 3, an inter-poly oxide layer 4, and a control gate 5 formed in sequence. Also, source and drain regions 6 and 7 are formed at opposed sides of the floating gate 3 and the control gate 5 in the p-type semiconductor substrate 1 by implantation of, e.g., n-type impurity ions.
In case of the stack type EEPROM cell, the floating gate 3 and the control gate 5 are stacked on the p-type semiconductor substrate 1. In this case, even though an area of the cell is relatively small, it may have a problem in that the erase function of the cell can be excessive. In such an excessive erase problem, the cell threshold may be shifted after many repeated write/erase cycles. In order to overcome the problem of the excessive erase function, the split gate type EEPROM cell has been proposed.
As shown in FIG. 2, a split gate type EEPROM cell according to the related art, a tunneling oxide layer 2 may be formed on a p-type semiconductor substrate 1, and a floating gate 3 is generally formed on a predetermined portion of the tunneling oxide layer 2. Then, an inter-poly oxide layer 4 is generally formed on the floating gate 3, and a select gate oxide layer 8 is formed at one side of the floating gate 3 on the p-type semiconductor substrate 1. After that, a control gate 5 may be formed on the inter-poly oxide layer 4 and the select gate oxide layer 8, where the inter-poly oxide layer 4 may be formed as one body (e.g., may be unitary) with the select gate oxide layer 8. Then, source and drain regions 6 and 7 are generally formed at opposed sides of the floating gate 3 and the control gate 5 in the (p-type) semiconductor substrate 1 by implantation of a high concentration or doping level of n-type impurity ions.
Accordingly, the split gate design makes it possible to solve the problem of the excessive erase function of the cell. However, the control gate 5 is formed not only on the floating gate 3 but also over the p-type semiconductor substrate 1, so that it can be difficult to decrease the area of the cell (or make it about the same size as the stacked gate structure). As a result, it may be difficult to satisfy the trend toward high integration in semiconductor devices containing EEPROM cells, particularly flash EEPROM cells.
In the related art split gate type (flash) EEPROM cell, a channel length of the control gate is generally formed or determined by an overlay control of photolithography. As a result, a threshold voltage and/or a cell current may be changed during operation of the cell. Also, since the control gate is formed along the surface of a wafer, it is highly desirable to consider overlay margins during scaling.